An important aspect of semiconductor integrated circuit (IC) performance is power consumption. The use of low power semiconductor ICs can allow battery powered electronic products to operate for longer periods of time, and/or allow the use of smaller batteries or smaller power supplies. Smaller batteries and power supplies can reduce the size, bulk and weight of electronic products.
A common semiconductor IC is the random access memory (RAM). RAMs store information for use by other circuits. The information can be stored within the RAM by a write operation, and the retrieved by a read operation. RAMs can be used in numerous electronic devices, in a standalone form (a RAM "chip"), in which the storing of information is the primary function of the device, or as one portion of a device having a larger function (often referred to as an "embedded" memory).
One of the primary sources of power consumption in many RAM devices is the sense operation within the RAM, and to a lesser extent, an operation referred to as bit line equalization. In order to understand sensing and bit line equalization, the operation of a prior art dynamic RAM (DRAM) will be described.
FIGS. 1 and 2 illustrate a DRAM read and refresh operation according to the prior art. In the read operation described, one bit of information is retrieved from the IC. Because the example set forth is that of a DRAM, the read operation is also a refresh operation. DRAMs require a refresh operation because the information stored within will "fade" over time unless it is periodically renewed.
Referring now to FIG. 1, a schematic diagram illustrating a DRAM architecture is set forth. The DRAM architecture is designated by the general reference character 100 and shown to include memory cells M0 and Mn. It is understood that a DRAM device could include literally millions of such memory cells, arranged in one or more arrays. The memory cells (M0 and Mn) are of conventional DRAM design, and include an n-channel "pass" transistor (N100 and N10n) and a storage capacitor (C100 and C10n). The storage capacitors (C100 and C10n) are the elements that actually store information. The amount of charge within a storage capacitor determines the information stored by the memory cell.
Each of the memory cells is coupled to a corresponding word line and bit line. For example, memory cell M0 is coupled to bit line /BL and word line WL0. Similarly, memory cell Mn is coupled to bit line BL and word line WLn. The bit lines BL and /BL form a bit line pair. Toward the top of FIG. 1, a bit line equalization circuit 102 is shown coupled to the bit line pair (BL and /BL). The bit line equalization circuit 102 includes an n-channel transistor N101, that is activated by a signal shown as EQ. Toward the bottom of the FIG. 1, a transfer gate circuit 104 is coupled to the bit line pair (BL and /BL). The transfer gate circuit 104 includes n-channel transistors N102 and N103 which are commonly activated by a signal shown as TG. The transfer gate circuit 104 connects the bit line pair (BL and /BL) to a sense amplifier 106. The sense amplifier 106 receives bit line voltages on first and second sense amplifier nodes (108 and 110).
The operation of the DRAM architecture 100 is best understood in conjunction with FIG. 2, which is a timing diagram illustrating the various control signals and voltage levels of the DRAM architecture 100 of FIG. 1. Prior to the initiation of a read cycle, the bit lines BL and /BL are "equalized" at a voltage that is between the positive power supply voltage, VDD, and the low power supply voltage, VSS. This voltage is shown as 1/2VDD. The read cycle illustrated by FIG. 2 begins with WL0 rising to a high voltage level. With word line WL0 high, pass transistor N100 within memory cell M0 is turned on, coupling capacitor C100 to bit line /BL. In the example of FIG. 2, it is assumed that capacitor C100 is charged (i.e., stores a positive charge), and so bit line /BL rises in potential, diverging in potential from bit line BL.
As the potential of the two bit lines (BL and /BL) diverge, the TG signal goes high, coupling the bit line pair (BL and /BL) to the sense amplifier circuit 106. The SA signal then goes high, activating the sense amplifier circuit 106 which drives the bit lines (BL and /BL) to opposite voltage according to the differential voltage on the bit line pair (BL and /BL). This is the operation that can consume considerable power. Because bit line /BL was higher than bit line BL, the bit line /BL is driven to the high power supply voltage (VDD) and the bit line BL is driven to the lower power supply voltage (VSS). Because the word line WL0 is still high, the VDD voltage on bit line /BL recharges (refreshes) storage capacitor C100. At the same time, the amplified voltage output from the sense amplifier circuit 106 can be output to other amplifiers, and eventually, an input/output (I/O) pin on the memory device. It is desirable to have the sense amplifier 106 drive the sense amplifier nodes (108 and 110) between the supply voltage levels (VDD and VSS), to provide the fastest driving capability, and thus the fastest sensing and refresh speeds.
After the capacitor C100 has been recharged, word line WL0 falls low to the voltage VSS. This turns off transistor N100, isolating capacitor C100 from the bit line, and trapping the charge stored therein.
The bit line equalization operation occurs once the sensing operation is complete (i.e., the bit lines have been driven to opposite supply voltage levels). In FIG. 1, the equalization function is performed by the equalization circuit 102. After the word line WL0 falls, the EQ signal pulses high. With the EQ signal high, transistors N101 is turned on. This action shorts the two bit lines (BL and /BL) together, and precharges the bit lines to the 1/2VDD voltage. It is understood that the sense amplifier circuit 106 also equalizes the sense amplifier nodes 108 and 110 to a 1/2VDD voltage level.
Thus, in the bit line equalization operation, bit line pairs charged at opposite supply voltage levels are shorted together, and at the same time, precharged to the 1/2VDD voltage. Because hundreds or even thousands of such bit line pairs are equalized at the same time, the equalization operation consumes considerable power. Further, because memory devices increase in size with each generation (i.e., 64 megabit (Mb) to 256 Mb and up), each new generation of memory devices can have more bit line pairs, and/or longer bit line pairs, than each previous generation.
Fortunately, at the same time bit line pairs and/or sizes have been increasing, transistor channel lengths have been decreasing, allowing for the use of lower power supply voltages. With lower power supply voltages, the bit lines pairs do not have to be driven to as high a voltage, resulting in less power consumption during the bit line equalization operation. There is a limit to the amount by which power supply voltages can be reduced. If power supplies are too low, the sense amplifiers will not be able to drive the bit lines fast enough, or to a high enough voltage level, to refresh memory cells in a sufficient amount of time.
In addition to high power consumption, conventional DRAMs having arrays which operate at supply voltage levels have other requirements that add to the complexity of the DRAM design. Referring back to FIG. 2, it is noted that when the word line WL0 and the TG signal initially go high, both signals exceed the high power supply VDD by an additional amount, designated as Vtn. This operation is often referred to as "booting." Booting is used to overcome the threshold voltage drop that would be introduced by n-channel transistors. Booted word lines provide a lower resistance path between the storage capacitors (C10n and C100) and their associated bit lines (BL and /BL), and during the refresh operation, allow the full level VDD signal to be coupled to the storage capacitor. Booted TG signals provide the same results with respect to the transfer gate circuit 104 devices.
A drawback to the use of booted signals is the additional circuitry that is required to provide a higher-than-supply signal. Booting could be eliminated by using a complementary metal-oxide-semiconductor (CMOS) transfer gate (a p-channel transistor and n-channel transistor in parallel, activated by complementary clock signals). Because the CMOS transfer gate has a p-channel device, no threshold drop would be introduced. While CMOS transfer gates could be used in the transfer gate circuit 104, such an implementation would increase the size of the transfer gate circuit 104. This same drawback makes CMOS transfer gates extremely impractical as substitutes for pass transistors in memory cells (as replacements for N10n and N100). The additional p-channel transistor for each memory cell in a semiconductor device having millions of such cells, would result in a large increase (as much as 33%) in the device size.
In addition to word line and transfer gate control signal "booting", there are other aspects of conventional DRAM design which should be taken into account when modifying a DRAM beyond conventional design approaches. The first is substrate biasing. In many conventional DRAM approaches, the substrate in which the DRAM is formed, is biased below the low power supply voltage. For example, if the lower power supply VSS were zero volts, the substrate would be "back-biased" at a negative voltage, VBB. The advantages provided by the substrate back-bias are best understood with reference to FIG. 3.
FIG. 3 is a side cross sectional view of a DRAM device 300 having a substrate 302 in which memory cells M300 and M301 are formed. The memory cells (M300 and M301) each include a pass transistor (N300 or N301) and a storage capacitor (C300 and C301). The memory cells are coupled to a bit line 304. The bit line 304 is coupled to the substrate 302 at a common n-type drain diffusion 306. A back-bias voltage advantageously increases the bias voltage across the common drain diffusion 306, more so than if the substrate was only at zero volts. The increase in bias voltage reduces the capacitance of the p-n junction formed by the diffusion 306, allowing the charge transferred from the storage capacitor to cause a larger voltage change on the bit line 304.
A second advantage of maintaining the substrate 302 at a back-bias voltage is reducing the likelihood of minority carrier injection from a storage capacitor to the substrate. The storage node of storage capacitor C300 310 is shown to be an n-type region within the substrate 302. For the purposes of this discussion, it is assumed that the storage capacitor C300 is storing a logic "0" (i.e., is discharged to VSS) and that the substrate is biased the VSS. In the event the substrate 302 rises above VSS (a condition referred to as substrate "bounce"), the p-n junction created by the n-type region of the storage node 310 can forward bias. Electrons (the minority carriers in this case) can be injected into the substrate 302. The charge on the storage capacitor C300 is thus altered, and can result in a data error when memory cell M300 is read. The substrate bounce condition can arise due to the inductance of conductors carrying the VSS supply to the substrate. If the substrate 302 were back biased, the substrate 302 would have to rise to a much higher potential in order to forward bias the storage node 310. Negative biasing of the substrate also increases the threshold voltage of pass transistors and thick field devices, which improves data integrity.
Yet another aspect of DRAM design that should be considered is the leakage introduced by the pass transistors (such as N10n and N100 of FIG. 1). In order to reduce any leakage from the charge stored on storage capacitors (such as C10n and C100) through the pass transistors, the threshold voltage of the pass transistors may be increased above the other n-channel transistors in the DRAM. As a result, when the pass transistors are turned off by the application of the low supply voltage (VSS) to their respective gates, leakage is reduced above and beyond the conventional n-channel transistors.
Reductions in DRAM power consumption could also be achieved by using a lower voltage in the array than in the other portions of the device. One way of providing the lower array voltage would be to use a non-booted TG signal. With a non-booted TG signal, when the sense amplifier is activated, one bit line would still be driven to the low VSS supply voltage, but the other bit line would be driven to a level of VDD-Vtn (where Vtn is the n-channel threshold voltage).
While reducing power consumption, such a reduction in array voltage can increase the common mode activity of the sense amplifier. With one bit line driven to the VSS voltage and the other driven to a VDD-Vtn voltage level, the bit lines will equalize to a voltage level of 1/2(VDD-Vtn). In contrast, the sense amplifiers typically equalize the sense amplifier nodes to the 1/2VDD voltage level. As a result, when the sense amplifiers are activated, the voltage at the sense amplifier nodes would include not only the differential voltage created by a memory cell coupled to the bit line pair, but also a common mode signal created by the difference in the different precharge voltages of the sense amplifier nodes and bit line pairs. This could lead to erroneous or slower sensing, or require more complex sense amplifier designs.
Thus, while unbooted transfer gates can be employed to reduce power consumption in a RAM device, such an approach has sensing drawbacks. It would be desirable to arrive at some way of reducing the power consumption of a RAM device, while at the same time, taking into account the various aspects of conventional RAM design, particularly DRAM design, discussed above.